1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More particularly, this invention relates to a semiconductor memory device which performs data input and output operation in synchronism with a clock signal.
2. Description of the Related Art
Dynamic Random Access Memory (DRAM) is an increasingly popular choice of memory device for use as a component in many of today's computer processors. One reason for this is its small size. A second reason for the popularity of DRAM today is its capacity for high speed operation. In particular, synchronous DRAM devices perform input/output operations in synchronism with a clock signal. This makes synchronous DRAM an ideal complement to the progressively faster processing units in computers today.
FIGS. 1 and 2 illustrate a conventional synchronous DRAM. The synchronous DRAM 100 has a clock buffer 1, a control signal latch circuit 2, a row address latch circuit 3, a column address latch circuit 4, a group of latch circuits 5, an output latch circuit 6, a command decoder 7, a memory cell array 8, an address buffer 9, a row decoder 10, a column decoder 11, a sense buffer and I/O gate 12, a data selector 13 and an output buffer 14.
The clock buffer 1 receives and temporarily holds a clock signal CLK output from an external clock generator (not shown), and supplies the clock signal CLK to the control signal latch circuit 2, the row address latch circuit 3, the column address latch circuit 4, the latch circuits 5 (see FIG. 2) and the output latch circuit 6.
The command decoder 7 receives control signals /RAS and /CAS and a write enable signal/WE, output from an external control circuit (not shown) such as a CPU, and outputs those signals to the control signal latch circuit 2. The control signal latch circuit 2 latches the individual control signals /RAS, /CAS and /WE and outputs them to a peripheral circuit (e.g., the output buffer 14) of the memory cell array 8 in response to the clock signal CLK.
The address buffer 9 receives an address signal AD from an external control circuit (not shown) and divides it into a row address signal and a column address signal. The address buffer 9 sends the row address signal to the row address latch circuit 3 and sends the column address signal to the column address latch circuit 4. The row address latch circuit 3 latches the row address signal in synchronism with the clock signal CLK and outputs the signal to the row decoder 10. The column address latch circuit 4 latches the column address signal in synchronism with the clock signal CLK and outputs it to the column decoder 11.
The row decoder 10 decodes the row address signal to produce a word line select signal and outputs this signal to the memory cell array 8. In accordance with this word line select signal, a specific word line is selected from a plurality of word lines in the memory cell array 8. The column decoder 11 decodes the column address signal to produce a bit line select signal and outputs this signal to the latch circuits 5. The latch circuits 5 latch the bit line select signal from the column decoder 11 in synchronism with the clock signal CLK, and output this select signal to the sense buffer and I/O gate 12.
The sense buffer and I/O gate 12 selects a specific column from a plurality of columns (each column consisting of a pair of bit lines) in the memory cell array 8 in response to the bit line select signal from the column decoder 11. The memory cell array 8 has the word lines, pairs of bit lines, and multiple memory cells connected to the word lines and the pairs of bit lines. In a reading operation from the memory cells, the sense buffer and I/O gate 12 first reads data signal from those memory cells in the memory cell array 8 selected by the individual select signals via the row decoder 10 and the column decoder 11. The sense buffer and I/O gate 12 then outputs the data signal to the data selector 13. The data selector 13 in turn outputs the cell data signal from the sense buffer and I/O gate 12 to the output latch circuit 6. The output latch circuit 6 latches the data output signal from the data selector 13 in synchronism with the clock signal CLK, and outputs this signal to the output buffer 14. The output buffer 14 outputs the read cell data signal as a read data signal Dout.
The synchronous DRAM 100 further has an input buffer and a write amplifier, neither illustrated. During writing operations, the write amplifier receives write data output from the external control circuit (not shown) via the input buffer and writes it to the memory cells selected by the address signal AD.
FIG. 2 shows the specific structures of the latch circuits 5, the sense buffer and I/O gate 12 and the memory cell array 8. The memory cell array 8 has a plurality of memory cells, a plurality of bit line pairs BL0 and /BL0 to BLn and /BLn, and a plurality of word lines WL. A plurality of memory cells 15 are respectively provided between each bit line pair and between word lines WL. One of the word lines WL is selected in accordance with the word line select signal from the row decoder 10.
The sense buffer and I/O gate 12 has a plurality of pairs of transfer transistors Tr0 to Trn and a sense buffer (or sense amplifier) 12a. The individual bit line pairs BL0 and/BL0 to BLn and/BLn are connected to data buses DB and /DB via the respective transfer transistor pairs Tr0 to Trn. The transfer transistor pairs Tr0 to Trn have gates connected to the output terminals (not shown) of individual latch circuits 5a to 5h (eight latch circuits in this example) that form the group of latch circuits 5. The latch circuits 5a-5h receive the select signal from the column decoder 11 and the clock signal CLK. In synchronism with this clock signal CLK, the individual latch circuits 5a-5h respectively send an output signal corresponding to the select signal from the column decoder 11 to the gates of the respective transfer transistor pairs Tr0-Trn. In response to this output signal, one pair of transfer transistors among the transfer transistor pairs Tr0-Trn turn on, allowing the cell 15 connected to the selected one word line WL to be read on the data buses DB and /DB via the associated bit line pair. The data buses DB and /DB are connected to the sense buffer 12a, which amplifies the cell data signal read on the data buses DB and /DB and outputs the amplified data signal to the data selector 13.
When data is read from the synchronous DRAM 100, the row address latch circuit 3, upon receiving the clock signal CLK, sequentially latches the row address signals output from the address buffer 9 and outputs them to the row decoder 10.
As shown in FIG. 3, upon reception of a first clock signal CLK.sub.2 which is one pulse of the clock signal CLK, the column address latch circuit 4 latches the column address signal from the address buffer 9 and outputs the signal to the column decoder 11. The column decoder 11 decodes the column address signal and sends a bit line select signal to the latch circuits 5.
Then, the latch circuits 5 latch the select signal from the column decoder 11 and send the latched signal to the sense buffer and I/O gate 12 in synchronism with a second clock signal CLK.sub.2. A memory cell 15 is selected in accordance with the select signals from the row decoder 10 and the column decoder 11, and a data signal is read from this memory cell. The sense buffer 12a amplifies the read data signal and sends it to the output latch circuit 6 via the data selector 13.
Next, the output latch circuit 6 latches the output data signal of the data selector 13 and outputs it to the output buffer 14 in synchronism with a third clock signal CLK.sub.3. The output buffer 14 in turn outputs the output data signal Dout.
The aforementioned latch circuits 3 to 6 latch signals and send them to the circuits 10, 11, 12 and 14 every period of the clock signal CLK. The output buffer 14 outputs a data signal Dout every time each of the latch circuits 3-6 performs the latching operation. The synchronous DRAM 100 performs a one-cycle reading operation at every third pulse of the clock signal CLK. As the latch circuits 3-6 latch signals in synchronism with the clock signal, stable signal transfer is possible. Consequently, the time for the signal transfer can be shortened by increasing the frequency of the clock signal CLK, thus improving the speed with which cell data signals can be read.
The above-described synchronous DRAM 100 however requires that the period of the clock signal CLK should be set with a period longer than a selected time interval such as the time t2 from when the latch circuits 5 latches the select signal to when the cell data signal output by the data selector 13 arrives at the output latch circuit 6. Nonetheless, time period t2, should approach or equal time period t1. This is because the operation of the DRAM during each period requires a single period of the clock signal CLK. In other words, the individual latch circuits 4 to 6 should be designed to match the time period t1 with the time period t2. The period t1 is a transfer time from when the latch circuit 4 latches the column address signal to when the select signal arrives at the latch circuits 5. The period t2 is a transfer time from when the latch circuits 5 latches the select signal to when the cell data signal output by the data selector 13 arrives at the output latch circuit 6.
Further, the synchronous DRAM 100 has the latch circuits 5a-5h between the column decoder 11 and the sense buffer and I/O gate 12, one for each column (bit line pair). This particular arrangement of the latch circuits 5a-5h increases the circuit area of the latch circuit group 5 and thus enlarges the chip (semiconductor integrated circuit).